1. Field of the Invention
This invention relates generally to the structure and fabrication process of MOSFET power devices. More particularly, this invention relates to a novel and improved MOSFET device structure and fabrication process wherein specially configured gates are formed to reduce the gate capacitance such that the speed of the MOSFET device is increased and devices can be manufactured with simplified method at lower cost while the device reliability is improved.
2. Description of the Prior Art
The goal of increasing the switching speed and meanwhile reducing the production cost of the MOSFET power device cannot be easily achieved. This is particularly true when the power MOSFET devices become more complicate both in cell structure and in device topology. In the meantime, in order to achieve higher switching speed, it is desirable to reduce the gate-to-drain capacitance. However, a device structure capable of providing such performance improvement typically involves the application of more complex fabrication processes. As the fabrication processes become more complex and increased number of masks are required, longer manufacture time cycles become necessary which leads to higher production costs. Complex fabrication processes with increased number of masks introduce further concerns. As more masks and processing steps are applied, more uncertainties of production yield and product reliability are introduced. The production costs are further impacted due to these undesirable factors. For these reasons, many technical improvements are attempted to improve the device performance to achieve higher switching speed while reducing the number of masks employed for MOSFET fabrication. Several MOSFET device structures and manufacture techniques are also disclosed in U.S. Patents.
In U.S. Pat. No. 5,404,040 entitled "Structure and Fabrication of Power MOSFETS including Termination Structures" (issued on Apr. 4, 1994), Hshieh et al. disclose a power MOSFET, as that shown in FIG. 1. The MOSFET is manufactured by a five mask process on a semiconductor body 2000 and 2001. A first insulating layer 2002 lies over the active and termination areas. A main polysilicon portion, 2003C and 2003B, lies over the first insulating layer largely above the active area. Also a first and second peripheral polysilicon segments 2003C1 and 2003C2 lie over the first insulating layer above the termination area which are etched as two separated segments with a separating gap 2013E. A gate electrode 2016 contacts the main polysilicon potion. Two source electrodes, 2015A and 2015B, are formed to contact the active area, the termination area and the first polysilicon segment 2003C1 through an opening in the second insulating layer 2012. The second polysilicon segment 2003C2 extends over a scribe line section of the termination area where the semiconductor is cut into separate dice. In this termination area, a metal portion is formed to contact this second polysilicon segment. During a dicing process, the second polysilicon segment and the metal portion are electrically shorted to the semiconductor body. The metal portion in combination of the second polysilicon segment are useful to equalize the potential at the outer peripheral of the MOSFET and reduces the likelihood of device malfunction.
The MOSFET as that shown in FIG. 1 presents several difficulties in the fabrication processes. Specifically, it is difficult to remove a silicon segment to form the gap 2013E for separating the first polysilicon segment 2003C1 from the second polysilicon segment 2013C2. If the gap 2013E is a small gap, then a wet etch process is not suitable due to its difficulties in controlling the etching dimensions. On the other hand, if a dry etch is applied in order to make the gap 2013E with a small gap-width, then the opening surface may be damaged as a result of dry etch process. In addition to the difficulties in manufacture, the structure in the termination area presents further difficulties and limitations. Due to the opening of this gap 2013E, a passivation layer is required to prevent mobile ions from entering into the device. As will be further discussed below, a requirement of applying a pad mask to define the passivation layer is necessary which results in more complicate manufacture processes and higher MOSFET production cost. Additionally, this configuration in the termination area causes a walk out phenomenon of the breakdown voltage. A more detail technical description will be provided below when a novel structural feature of this invention is disclosed to improve the termination configuration in order to resolve the walkout problems.
In another U.S. Pat. No. 5,268,586, entitled "Vertical Power MOS Device with Increased Ruggedness and Method of Fabrication", (issued on Dec. 7, 1993) Mukherjee et al. disclose a semiconductor device with improved ruggedness by forming a second body region, i.e., a second base region, within the first body region, under the source regions. As shown in a cross sectional view of FIG. 2A, the second body region is shallower than the first body region and is formed close to the channel region to reduce the parasitic resistance in the first body region. The lateral edges of the second body region are substantially aligned with the lateral edges of the gate electrode. The first body region and the source region are formed by sequential implantation through the polysilicon gate electrode using the polysilicon gate electrode as a self aligned mask. The second body region is then formed by body implantation, again, using the polysilicon gate as the implant mask, without substantial lateral diffusion. Since the second body region is formed without substantial lateral diffusion, very limited thermal budget is allowed for the this second body region. Reduction of the drain to source resistance is quite limited because, without enough diffusion process, this second body region is formed with reduced depth under the source regions. Furthermore, high contact resistance between the metal and the body region may occur due to a low P+ surface doping concentration as the net dopant concentration as a function of depth along the line A-A' shown in FIG. 2B. Additional difficulties of higher threshold voltage may also arise from lateral diffusion of the second body region to touch the channel region. Finally, a polysilicon layer of greater thickness employed in this structure may cause another problem. For high density DMOS device, poor metal coverage may occur when the re-firing of the thicker polysilicon layer to block the high energy body implant ions causes the contact openings to have high aspect ratio, i.e., high height to width ratio.
In another U.S. Pat. No. 5,273,922, entitled "High Speed Low Gate/Drain Capacitance DMOS Device", (issued on Dec. 28, 1993), as that shown in FIG. 3, Tsoi discloses a DMOS device with field oxide in the channel between adjacent transistors and an impurity implanted through the same opening in which the field oxide is formed. The gate is deposited over the field oxide and spaced from the supporting epitaxial layer by the field oxide to reduce the gate-to-drain capacitance. The implant impurity blow the field oxide reduce the on-resistance of the device. With these advantages achievable by Tsoi's DMOS device, it is however limited by a difficulty that the size of the transistors can not be further reduced to increase the cell density. The lateral dimension of a transistor cell is limited by a misalignment tolerance between the polysilicon gate and the field oxide. In order to avoid an increase in the device threshold voltage, the body regions must be kept at a certain distance away from the field oxide areas. However, since the body implant is not self aligned to the field oxide, sufficient space has to be allowed to accommodate potential misalignment errors within the alignment tolerances. The lateral dimensions of the transistor are prevented from being further reduced due to this requirement
Therefore, there is still a need in the art of power device fabrication, particularly for DMOS design and fabrication, to provide a structure and fabrication process that would resolve these difficulties.